1. Field of the Invention
The present invention relates to electronic devices, and more specifically to low-power, high-speed execution of algorithms in logic gates within electronic devices.
2. Description of Related Art
The majority of modern microprocessors are designed using a circuit family known as CMOS. In practice, CMOS circuits consume power only when switching states. CMOS consists of two kinds of transistors: P-channel and N-channel field effect transistors, or PFETs and NFETs, typically fabricated in roughly equal numbers on a common substrate. Static CMOS logic gates are constructed so that either the PFETs or the NFETs conduct, creating a path either to power or to ground, respectively. Except for the transient when the transistors are switching, PFETs and NFETs in a static CMOS circuit do not both conduct simultaneously. A CMOS logic gate consumes practically no DC power, and consumes AC power only when switching.
Since most chips initially constructed using this technology are slow by today""s standards (one megahertz or less), most of the time signals were not switching, so the power consumed by a CMOS circuit was very low. Many portable devices were made possible by this technology. CMOS gained rapid favor for its ease of construction and simple design rules, as well as its tolerance for noise.
However, current applications of CMOS technology commonly run at very high clock rates of 200 megahertz or more. Ignoring technology differences, a circuit that used to bum little power at 1 megahertz will burn 200 times that amount when it is run at 200 MHz. Designing systems that incorporate processors and support logic that consume this much power is a problem, both in getting the power in, and getting the resulting heat out.
One well-known CMOS design style with little DC power consumption is the non-inverting dynamic logic family. Non-inverting dynamic logic gates include an internal xe2x80x9cevaluatexe2x80x9d node that is precharged during one portion of a clock cycle, and then may (depending on input values) be discharged during a later portion of the clock cycle. The evaluate node then provides its voltage as an output from the logic gate. The power consumption of a dynamic CMOS circuit is equal to fCL(VDDxe2x88x92VSS)2, where f is the frequency, CL is the switching capacitance, and VDDxe2x88x92VSS defines the switching voltage range.
Another logic family with little DC power consumption is the new N-NARY logic family. N-NARY logic is more fully described in the co-pending application, U.S. Pat. App. Ser. No. 09/019,278, filed Feb. 5, 1998, entitled xe2x80x9cMethod and Apparatus for a 1 of N Signalxe2x80x9d (hereinafter xe2x80x9cN-NARY Patentxe2x80x9d), which is incorporated by reference into this application. Due to the nature of the N-NARY style, various implementations for a given logic function exist, each of which differs in the structure of the N-tree. Different N-tree structures may have different amounts of parasitic capacitance, and thus different performance characteristics. It is the parasitic capacitance of the N-tree structure that slows down the evaluate transition of the logic gate.
The effect of parasitic or unwanted capacitance on gate speed is often difficult to quantify because there are actually two factors involved. The first (and more straightforward) factor is the amount of extra charge stored on the parasitic capacitance. The second factor, which is more difficult to quantify, is the additional amount of time it takes to conduct this additional charge to ground. This amount of time is related to the effective resistance of the path that is discharging the parasitic capacitance. The effective resistance is difficult to estimate because of the non-linear nature of the resistance of the transistors conducting the charge. The presence of extra charge in an N-tree causes higher voltages on the sources and drains of the transistors involved in conducting the charge to ground. Thus, the gate-source voltage of these transistors is reduced and their conductivity is degraded.
In general, it is most desirable to reduce parasitic capacitance that has a relatively long discharge path to ground. This is because the charge associated with this kind of capacitance will have the longest lasting effect on the conductivity of the transistors attempting to discharge the path. Of course, reducing any parasitic capacitance is beneficial, but sometimes a designer has to make a choice about which particular capacitance to reduce in a gate.
Another important effect of parasitic capacitance in CMOS logic gates and especially in dynamic logic gates is the unintended discharge of a node via charge sharing. In this case a certain node (such as the top of an N-tree stack) is intended to stay at a high voltage (i.e., not discharge). However, the node can be partially or largely discharged by having its charge drawn away by a parasitic capacitance with a lower voltage that is switched on to the node in question. The amount of voltage loss is related to the relative amounts of charge on the nodes involved in the transaction. Charge sharing is minimized by either ensuring the parasitic capacitance is at a benign voltage level or by minimizing the size of the parasitic capacitance.
Parasitic capacitance in CMOS gates comes from various sources. One source is the capacitance of the wires that connect together the various transistors in the gate. Another source is the transistor source/drain capacitance associated with each transistor. Source drain capacitance is present whether a gate is turned on or off Another source is the channel capacitance of a transistor. This is the capacitance of the channel region of a transistor that is turned on or is in the conducting state. In addition to these static capacitance sources, the voltage waveforms on transistor gates can couple charge onto the source/drain nodes of transistors. Specifically, when a dynamic gate input rises, positive charge is transferred from the gate to this transistor""s source and drain regions.
The parasitic capacitance presented by the drain of a transistor that is in the on state is large because it is comprised of that transistor""s drain capacitance, its channel capacitance, the source capacitance (seen xe2x80x9cthroughxe2x80x9d the gate) and whatever other capacitance is attached to that transistor""s source terminal. This is because the transistor drain and source terminals are connected by the resistance of the channel when the transistor is in the on state. Because of this, it is important to keep the parasitic transistors attached to an evaluate or discharge path turned off.
Capacitance isolation is the technique of improving gate delay and reducing charge sharing by isolating parasitic or unwanted capacitance from the part of the gate circuit actively involved in switching an output. This technique can be exploited to a great degree in the new N-NARY logic family to reduce gate size, improve gate speed, and reduce the severity of unwanted charge sharing. In particular, while not obvious, it is often possible to reduce unwanted parasitics in N-NARY gates by adding transistors in a judicious way, thereby increasing gate speed and/or overall gate area. The extent to which this design tradeoff may be made is unique to the N-NARY encoding of signals in this logic family.
The capacitance isolation technique discussed herein is notas applicable to traditional static CMOS logic because of the complimentary nature of the p- and n-transistor networks in a traditional CMOS gate. In the general case, the transistors that are the compliment of the active or conducting transistors have parasitic capacitance that is exposed to the output of the gate. PMOS transistors in particular have significant parasitic capacitance due to their larger size.
The technique is also applicable to traditional dual-rail dynamic logic, though the opportunities are not as great as in general N-NARY dynamic logic due to the larger fraction of turned-off transistors in general N-NARY logic.
The present invention comprises a logic device with improved capacitance isolation, and a design methodology that reduces parasitic capacitance, allowing designers to achieve specific design timing and output goals with smaller circuits. The logic device further comprises a virtual ground node that is electrically coupled to ground during the evaluation cycle, a plurality of input signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors wherein each transistor is gated by one of the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, each input signal further comprises an input wire ozone or more N-NARY input signals. In one embodiment, the discharge paths are perfectly isolated from each other during the evaluation cycle for every possible combination of the input signals. In another embodiment, the discharge paths further comprise an evaluation path and a non-evaluation path. In this embodiment, the non-evaluation path further comprises an evaluate node and at least two intermediate nodes where one of the intermediate node is coupled to the virtual ground node. During the evaluation cycle for at least one combination of said input signals, the evaluate node of the non-evaluation path is electrically isolated from the evaluation path and the two intermediate nodes are electrically coupled to the evaluation path.